As electronic devices become smaller, the need for innovative packaging configurations for semiconductor chips becomes increasingly important. Many of these configurations seek to minimize connections and lead space necessary for the connections. In doing this, these packaging configurations expose conductors or bit lines of the chip circuitry on or near the chip surface and beneath protective layers that cover the chip. The different chip packaging techniques that have bit lines at or near the chip surface include techniques known as "on-chip routing," "lead-over-chip" packaging, and "flip-chip" packaging. In all of the configurations resulting from these techniques, a surface covering often protects the exposed bit lines. The surface covering often is composed of two materials. One material may be a kapton or polyimide tape, and the other may be a bonding or molding compound.
In lead-over-chip packing, for example, a lead frame to the chip circuit may be placed over the surface covering and the bit lines. The lead frame and surface covering materials may adversely affect signals existing in bit lines beneath these materials. One way in which these surface materials may adversely affect signals in bit lines near the chip surface is by dielectrically coupling the electrical signals passing through the bit lines with the lead frame and the materials of the surface covering. If there are multiple bit lines near the surface of the electronic device and one of the surface covering materials affects certain of these bit lines more so than certain other bit lines, differential dielectric coupling may occur to adversely affect signals flowing through the bit lines. This phenomenon may be thought of as "differential dielectric coupling" of the various bit lines with the associated surface covering materials.
The lead-over-chip packaging technique provides an example to more clearly illustrate differential dielectric coupling of bit lines with surface covering materials. The dielectric constant of the polyimide tape may be approximately 3.5, while that of the molding compound may be approximately 5.0. Electrically coupled noise into the bit lines from the lead frame that is placed over the polyimide tape and the molding compound on the chip occurs if this vertical boundary falls between any differential bit line set. This is caused by the imbalance in capacitive coupling from the lead frame to each bit line through the different dielectric paths of the polyimide tape and molding compound.
The problem of differential dielectric coupling becomes even more serious when packaging material fabrication techniques become increasingly precise. As this occurs, boundaries between covering materials become more well-defined. If these more well-defined boundaries fall between bit lines, for example, between parallel bit lines on the semiconductor device surface, differential coupling can become an important source of electrical noise for signals passing through the bit lines.
As a result of the above, there is a need for a method to package an integrated circuit chip that reduces electrical noise from vertical dielectric boundaries in configurations where a conductor structure on the device appears near the chip surface.
There is a need for a method and configuration to eliminate electrical noise due to differential dielectric coupling from different packaging materials that form vertical dielectric boundaries in a variety of packaging techniques, including on-chip routing, lead-over-chip packaging, and flip-chip packaging.
There is a need for a method and configuration that eliminate electrically coupled noise due to differentially coupling bit lines with the lead frame and other chip surface materials that have different dielectric properties.